DSP Chip Design of Digital Audio Reverberator

碩士 === 國立交通大學 === 電機與控制工程系所 === 93 === Abstract In order to improve the sense of reality of listening experience, souranding and room effect, this thesis focusing on audio room effect simulation and hardware implementataion of a signal processor is proposed. The algorithm used in this thesis is base...

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Bibliographic Details
Main Authors: KUO HUI CHEN, 郭慧貞
Other Authors: ctlin
Format: Others
Language:zh-TW
Published: 2004
Online Access:http://ndltd.ncl.edu.tw/handle/82715393561475046039
Description
Summary:碩士 === 國立交通大學 === 電機與控制工程系所 === 93 === Abstract In order to improve the sense of reality of listening experience, souranding and room effect, this thesis focusing on audio room effect simulation and hardware implementataion of a signal processor is proposed. The algorithm used in this thesis is based on the phenomenon that different audio spaces have different impulse responses. With perticular space parameter,a specific audio room effect is synthetized by signal processor even in multichannel sound system. This algorithm is realized in proposed 24-bit Low-Cost Processor (LCP24) with optimized machine code. In this thesis, the reverberator proposed by Schroeder and Moorer is adopted and modified. These two reverberators include four parallel Comb filters and two all-pass filters in series to generate direct signal, early reflection, and fused reverberation. In order to implement a real-time audio room effect system with LCP24, the reverberator is modified by adding a FIR filter in front of the four parallel filters. A low-pass filter is added to increase the listening space. The modified model is more accurate than original one. For real-time operations, software and hardware are optimized with each other. For LCP24 implementation, the trade off of speed and area is optimized by minimized intructinon set and five-stage pipeline. In LCP24, there are two memories for vector operation, four loops, temporary address memories for returning from subprogram, 24 bits precision floating point operation unit,integer operation unit. It also supports parallel operation of multiplication and summation in a single operation cycle by MAC command and special addressing mode. The chip can be synthesized by COMPASS cell library and realized in UMC 0.18μm 1P6M CMOS technology. The clock rate of the chip is expected to be 100 MHz proved by post-layout simulation and the silicon area required for the core is approximately 6.5 mm2.