Showing 41 - 60 results of 105 for search 'Kuen-Jong Lee', query time: 0.11s Refine Results
  1. 41
    DASTEP:A Design Automation System for System-on-Chip Test Platform
    by Wen-Cheng Huang, 黃文成
    Published 2006
    Other Authors: “...Kuen-Jong Lee...”
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  2. 42
    Software-Based Test Methodology for Fully Associative Data Cache
    by Hung-Min Hsu, 許宏銘
    Published 2006
    Other Authors: “...Kuen-Jong Lee...”
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  3. 43
    PROTOTYPING OF SOC TEST PLATFORM AND ITS APPLICATION TO DESIGN AND TEST VERIFICATION
    by Ming-Dian Kuo, 郭明典
    Published 2006
    Other Authors: “...Kuen-Jong Lee...”
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  4. 44
    Software-Based Testing for ARM9-Compatible Embedded Processor
    by Kuen-Yi Huang, 黃琨懿
    Published 2006
    Other Authors: “...Kuen-Jong Lee...”
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  5. 45
    Design and Diagnosis of High Speed Pipelined A/D Converters
    by Chih-Haur Huang, 黃志豪
    Published 2004
    Other Authors: “...Kuen-Jong Lee...”
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  6. 46
    Design and Automatic Generation for Universal Memory Built-In Self-Test System
    by Yi-Wei Chang, 張逸偉
    Published 2004
    Other Authors: “...Kuen-Jong Lee...”
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  7. 47
    Design Automation for Advanced Scan Architecture
    by Yao-Ching Chiang, 蔣耀慶
    Published 2004
    Other Authors: “...Kuen-Jong Lee...”
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  8. 48
    Design and Test of Embedded Processors Based on ARM9 Structure
    by Tsuei-Ling Hsieh, 謝翠玲
    Published 2004
    Other Authors: “...Kuen-Jong Lee...”
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  9. 49
    Framework Design For System-on-a-Chip Test Platform
    by Chia-Yi Chu, 朱家頤
    Published 2004
    Other Authors: “...Kuen-Jong Lee...”
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  10. 50
    Design and Test of Discrete Cosine Transform Circuits
    by You-Chung Lin, 林友中
    Published 2003
    Other Authors: “...Kuen-Jong Lee...”
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  11. 51
    Power Reduction with Multiple Capture Orders
    by Shaing-Jer Hsu, 徐祥哲
    Published 2003
    Other Authors: “...Kuen-Jong Lee...”
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  12. 52
    Advanced Scan Architecture for Test Time and Test Volume Reductions
    by Chia-Kai Yang, 楊家凱
    Published 2003
    Other Authors: “...Kuen-Jong Lee...”
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  13. 53
    An SOC Test Platform Supporting ADC BIST
    by Chun-Hen Chang, 張浚恆
    Published 2003
    Other Authors: “...Kuen-Jong Lee...”
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  14. 54
    Test Application Time and Power Reduction Techniques for Scan-Based Circuits
    by Jih-Jeen Chen, 陳繼展
    Published 2003
    Other Authors: “...Kuen-Jong Lee...”
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  15. 55
    A Hybrid Method on Functional Testing for Embedded Processor Cores
    by Min-Chien Chen, 陳旻謙
    Published 2003
    Other Authors: “...Kuen-Jong Lee...”
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  16. 56
    Control and Observation Structures of Analog Circuits and Built-In Self-Test Designs for D/A and A/D Converters
    by Yun-Che Wen, 溫昀哲
    Published 2001
    Other Authors: “...Kuen-Jong Lee...”
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  17. 57
    Testing on the ADC and DAC
    by Chao-Yi Chen, 陳朝義
    Published 2001
    Other Authors: “...Kuen-Jong Lee...”
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  18. 58
    PLL with On-Chip Jitter Measurement
    by Jun-Jia Chen, 陳俊嘉
    Published 2001
    Other Authors: “...Kuen-Jong Lee...”
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  19. 59
    A Test Scheduling Model for System-On-A-Chip Design
    by He-Jie Juang, 莊賀傑
    Published 2001
    Other Authors: “...Kuen-Jong Lee...”
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  20. 60
    Testable Design of ARM Based Core
    by Yu-Yuan Tzeng, 曾裕淵
    Published 2001
    Other Authors: “...Kuen-Jong Lee...”
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