Showing 21 - 40 results of 69 for search 'Shih-Hsu Huang', query time: 0.19s Refine Results
  1. 21
    Resource Binding of High-Speed Low-Power Nonzero Clock Skew Circuits
    by Chun-Hua Cheng, 程駿華
    Published 2009
    Other Authors: “...Shih-Hsu Huang...”
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  2. 22
    Minimum-Power Gated Clock Tree Design
    by Jia-Hong Jian, 簡嘉宏
    Published 2009
    Other Authors: “...Shih-Hsu Huang...”
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  3. 23
    Reliability Oriented Multiple-Vth Assignment for Leakage Power Reduction
    by Shih-Wei Wu, 吳世偉
    Published 2008
    Other Authors: “...Shih-Hsu Huang...”
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  4. 24
    Low Power Clock Gating with Aging Skew Considered
    by Song-Bin Pan, 潘松濱
    Published 2008
    Other Authors: “...Shih-Hsu Huang...”
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  5. 25
    Race-Condition-Aware Sequential Timing Optimization
    by Yow-Tyng Nieh, 聶佑庭
    Published 2008
    Other Authors: “...Shih-Hsu Huang...”
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  6. 26
    Adjustable Coefficient Infinite Impulse Response Filter Design
    by Chih-Kuang .Chien, 簡志光
    Published 2005
    Other Authors: “...Shih-Hsu Huang...”
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  7. 27
    Downlink Base Transmit Station Modulator Design in WCDMA System
    by KAI-HAO PAI, 白鎧豪
    Published 2005
    Other Authors: “...Shih-Hsu Huang...”
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  8. 28
    Asynchronous FIFO design
    by Chih-Ming Chiang, 江志明
    Published 2005
    Other Authors: “...Shih_Hsu Huang...”
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  9. 29
    A Post-Processing Approach to Minimize TSV Number in High-Level Synthesis
    by Tsorng-Yu Huang, 黃琮淯
    Published 2010
    Other Authors: “...Shih-Hsu Huang...”
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  10. 30
    A Minimum Buffer Insertion Approach for Clock Period Minimization
    by Guan-Yu Jhuo, 卓冠宇
    Published 2010
    Other Authors: “...Shih-Hsu Huang...”
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  11. 31
    Zero Skew Clock Tree Synthesiswith Multi-Voltage Consideration
    by Wei-Lun Huang, 黃偉倫
    Published 2010
    Other Authors: “...Shih-Hsu Huang...”
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  12. 32
    Clock Design Methodology for High Reliability
    by Chia-Ming Chang, 張家銘
    Published 2010
    Other Authors: “...Shih-Hsu Huang...”
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  13. 33
    TSV Count Minimization through Alternative Paths
    by Chih-Hsien Kuo, 郭致顯
    Published 2011
    Other Authors: “...Shih-Hsu Huang...”
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  14. 34
    Layer Assignment for TSV Number Minimization Using Multiplexer Sharing in 3D IC Design
    by Yen-Hsin Lee, 李彥勳
    Published 2011
    Other Authors: “...Shih-Hsu Huang...”
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  15. 35
    Peak Current Minimization for Activity Driven Gated Clock Tree
    by Shih-Ji Wang, 王詩集
    Published 2012
    Other Authors: “...Shih-Hsu Huang...”
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  16. 36
    TSV Number Minimization by Stacking Selection
    by Wei-Shuo Tzeng, 曾韋碩
    Published 2012
    Other Authors: “...Shih-Hsu Huang...”
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  17. 37
    Clock Tree Design Using Self-Correcting Adjustable Delay Buffers
    by Hsin-Heng Lu, 盧信亨
    Published 2013
    Other Authors: “...Shih-Hsu Huang...”
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  18. 38
    A High Speed Fuzzy Inference Processor with the Capability of Rule Analyzing
    by Shi-Zhi Liu, 劉時誌
    Published 2003
    Other Authors: “...Shih-Hsu Huang...”
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  19. 39
    A Study on the Hardware Design of High Speed Fuzzy Inference Processor
    by Chien-Yuan Lai, 賴建元
    Published 2002
    Other Authors: “...Shih-Hsu Huang...”
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  20. 40
    A Floorplan-Based Power Distribution Network Design Automation System
    by Chu-Liao Wang, 王主料
    Published 2002
    Other Authors: “...Shih-Hsu Huang...”
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