Showing 61 - 69 results of 69 for search 'Shih-Hsu Huang', query time: 0.16s Refine Results
  1. 61
    3D IC Memory BIST Design and Test Scheduling under Power Constraints
    by Yen-Chun Ko, 柯妍君
    Published 2017
    Other Authors: “...Shih-Hsu Huang...”
    Get full text
    Others
  2. 62
    On-chip-variation-aware Power-mode-aware Buffer Synthesis
    by Yu Lee, 李豫
    Published 2017
    Other Authors: “...Shih-Hsu Huang...”
    Get full text
    Others
  3. 63
    Retiming Transformation with Considering Race Conditions
    by Feng-Pin Lu, 呂逢彬
    Published 2005
    Other Authors: “...Shih-Hsu Huang...”
    Get full text
    Others
  4. 64
    A Formal Approach to the Slack Driven Scheduling Problem in High Level Synthesis
    by Chun-Hua Cheng, 程駿華
    Published 2005
    Other Authors: “...Shih-Hsu Huang...”
    Get full text
    Others
  5. 65
    3D IC Test Scheduling with Re-Distribution Layer Routing Considered
    by Cheng-Hsun Nien, 粘丞勛
    Published 2015
    Other Authors: “...Shih-Hsu Huang...”
    Get full text
    Others
  6. 66
    Utilizing Idle Functional Units for Maximizng The Number of IP Watermarks
    by Tsung-Tang Lin, 林琮棠
    Published 2015
    Other Authors: “...Shih-Hsu Huang...”
    Get full text
    Others
  7. 67
    Design Methodologies for Speeding up the Development of 3D ICs and Electronic System-Level Designs
    by Hua-Hsin Yeh, 葉驊昕
    Published 2015
    Other Authors: “...Shih-Hsu Huang...”
    Get full text
    Others
  8. 68
    On-Chip-Variation-Aware Top-Level Gated Clock Tree Synthesis
    by Te-Jui Wang, 王得睿
    Published 2016
    Other Authors: “...Shih-Hsu Huang...”
    Get full text
    Others
  9. 69
    Co-Optimization of Memory BIST Grouping and Test Scheduling under Power Constraints
    by Chang-Han Yeh, 葉昌翰
    Published 2016
    Other Authors: “...Shih-Hsu Huang...”
    Get full text
    Others
Search Tools: Get RSS Feed — Email this Search