Integrated Design Validation: Combining Simulation and Formal Verification for Digital Integrated Circuits
The correct design of complex hardware continues to challenge engineers. Bugs in a design that are not uncovered in early design stages can be extremely expensive. Simulation is a predominantly used tool to validate a design in industry. Formal verification overcomes the weakness of exhaustive simul...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
International Institute of Informatics and Cybernetics
2006-04-01
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| Series: | Journal of Systemics, Cybernetics and Informatics |
| Subjects: | |
| Online Access: | http://www.iiisci.org/Journal/CV$/sci/pdfs/P457798.pdf
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