An Efficient Method of Parallel Multiplication on a Single DSP Slice for Embedded FPGAs
Field-programmable gate arrays (FPGAs) can efficiently implement custom applications via their embedded digital signal processor (DSP) slices, including binary multipliers. An increasing number of binary multipliers belonging to a DSP slice usually demonstrate that it has the capacity to process as...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2019-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/8772177/ |