A 4-bit 36 GS/s ADC with 18 GHz Analog Bandwidth in 40 nm CMOS Process

A 4-bit 36 GS/s ADC with 18 GHz Analog Bandwidth in 40 nm CMOS Process

This paper presents a 4-bit 36 GS/s analog-to-digital converter (ADC) employing eight time-interleaved (TI) flash sub-ADCs in 40 nm complementary metal-oxide-semiconductor (CMOS) process. A wideband front-end matching circuit based on a peaking inductor is designed to increase the analog input bandw...

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Bibliographic Details
Main Authors: Hanbo Jia, Xuan Guo, Xuqiang Zheng, Xiaodi Xu, Danyu Wu, Lei Zhou, Jin Wu, Xinyu Liu
Format: Article
Language:English
Published: MDPI AG 2020-10-01
Series:Electronics
Subjects:
analog-to-digital converter
flash ADC
time-interleaved
comparator offset calibration
timing mismatch calibration
Online Access:https://www.mdpi.com/2079-9292/9/10/1733

Internet

https://www.mdpi.com/2079-9292/9/10/1733

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