Decimal multiplication using compressor based-BCD to binary converter
The objective of this work is to implement a scalable decimal to binary converter from 8 to 64 bits (i.e 2-digit to 16-digit) using parallel architecture. The proposed converters, along with binary coded decimal (BCD) adder and binary to BCD converters, are used in parallel implementation of Urdhva...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Elsevier
2018-02-01
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| Series: | Engineering Science and Technology, an International Journal |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2215098617312181 |