Design and implementation of UVM verification platform based on C_Model

As the scale and complexity of integrated circuits increase, the verification work becomes more and more complex and important. The verification cycle has reached or exceeded 70% of the entire chip design cycle. Therefore, it is urgent to find an efficient verification method to improve verification...

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Bibliographic Details
Main Authors: Zhang Jing, Bu Gang
Format: Article
Language:zho
Published: National Computer System Engineering Research Institute of China 2019-10-01
Series:Dianzi Jishu Yingyong
Subjects:
uvm
Online Access:http://www.chinaaet.com/article/3000109594