Design and implementation of embedded hardware accelerator for diagnosing HDL-CODE in assertion-based verification environment
The use of assertions for monitoring the designer’s intention in hardware description language (HDL) model is gaining popularity as it helps the designer to observe internal errors at the output ports of the device under verification. During verification assertions are synthesised and the generated...
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| Format: | Article |
| Language: | English |
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University of Maiduguri
2013-08-01
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| Series: | Arid Zone Journal of Engineering, Technology and Environment |
| Online Access: | http://azojete.com.ng/index.php/azojete/article/view/155/130 |