An Approach to the Construction of a Network Processing Unit
The paper proposes the architecture and basic requirements for a network processor for OpenFlow switches of software-defined networks. An analysis of the architectures of well-known network processors is presented − NP-5 from EZchip (now Mellanox) and Tofino from Barefoot Networks. The advantages an...
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Yaroslavl State University
2019-03-01
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Online Access: | https://www.mais-journal.ru/jour/article/view/1161 |
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doaj-a9e27d50fdeb452c9f97fd01f676a6ba2021-07-29T08:15:15ZengYaroslavl State UniversityModelirovanie i Analiz Informacionnyh Sistem1818-10152313-54172019-03-01261396210.18255/1818-1015-2019-1-39-62892An Approach to the Construction of a Network Processing UnitStanislav O. Bezzubtsev0Vyacheslav V. Vasin1Dmitry Yu. Volkanov2Shynar R. Zhailauova3Vladislav A. Miroshnik4Yuliya A. Skobtsova5Ruslan L. Smeliansky6Applied Research Center for Computer NetworksApplied Research Center for Computer NetworksLomonosov Moscow State UniversityLomonosov Moscow State UniversityLomonosov Moscow State UniversityLomonosov Moscow State UniversityLomonosov Moscow State UniversityThe paper proposes the architecture and basic requirements for a network processor for OpenFlow switches of software-defined networks. An analysis of the architectures of well-known network processors is presented − NP-5 from EZchip (now Mellanox) and Tofino from Barefoot Networks. The advantages and disadvantages of two different versions of network processor architectures are considered: pipeline-based architecture, the stages of which are represented by a set of general-purpose processor cores, and pipeline-based architecture whose stages correspond to cores specialized for specific packet processing operations. Based on a dedicated set of the most common use case scenarios, a new architecture of the network processor unit (NPU) with functionally specialized pipeline stages was proposed. The article presents a description of the simulation model of the NPU of the proposed architecture. The simulation model of the network processor is implemented in C ++ languages using SystemC, the open-source C++ library. For the functional testing of the obtained NPU model, the described use case scenarios were implemented in C. In order to evaluate the performance of the proposed NPU architecture a set of software products developed by KM211 company and the KMX32 family of microcontrollers were used. Evaluation of NPU performance was made on the basis of a simulation model. Estimates of the processing time of one packet and the average throughput of the NPU model for each scenario are obtained.https://www.mais-journal.ru/jour/article/view/1161network processornetwork processing unitswitchcomputer networkssdncomputer architecturesimulation modelingopen flow protocol |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Stanislav O. Bezzubtsev Vyacheslav V. Vasin Dmitry Yu. Volkanov Shynar R. Zhailauova Vladislav A. Miroshnik Yuliya A. Skobtsova Ruslan L. Smeliansky |
spellingShingle |
Stanislav O. Bezzubtsev Vyacheslav V. Vasin Dmitry Yu. Volkanov Shynar R. Zhailauova Vladislav A. Miroshnik Yuliya A. Skobtsova Ruslan L. Smeliansky An Approach to the Construction of a Network Processing Unit Modelirovanie i Analiz Informacionnyh Sistem network processor network processing unit switch computer networks sdn computer architecture simulation modeling open flow protocol |
author_facet |
Stanislav O. Bezzubtsev Vyacheslav V. Vasin Dmitry Yu. Volkanov Shynar R. Zhailauova Vladislav A. Miroshnik Yuliya A. Skobtsova Ruslan L. Smeliansky |
author_sort |
Stanislav O. Bezzubtsev |
title |
An Approach to the Construction of a Network Processing Unit |
title_short |
An Approach to the Construction of a Network Processing Unit |
title_full |
An Approach to the Construction of a Network Processing Unit |
title_fullStr |
An Approach to the Construction of a Network Processing Unit |
title_full_unstemmed |
An Approach to the Construction of a Network Processing Unit |
title_sort |
approach to the construction of a network processing unit |
publisher |
Yaroslavl State University |
series |
Modelirovanie i Analiz Informacionnyh Sistem |
issn |
1818-1015 2313-5417 |
publishDate |
2019-03-01 |
description |
The paper proposes the architecture and basic requirements for a network processor for OpenFlow switches of software-defined networks. An analysis of the architectures of well-known network processors is presented − NP-5 from EZchip (now Mellanox) and Tofino from Barefoot Networks. The advantages and disadvantages of two different versions of network processor architectures are considered: pipeline-based architecture, the stages of which are represented by a set of general-purpose processor cores, and pipeline-based architecture whose stages correspond to cores specialized for specific packet processing operations. Based on a dedicated set of the most common use case scenarios, a new architecture of the network processor unit (NPU) with functionally specialized pipeline stages was proposed. The article presents a description of the simulation model of the NPU of the proposed architecture. The simulation model of the network processor is implemented in C ++ languages using SystemC, the open-source C++ library. For the functional testing of the obtained NPU model, the described use case scenarios were implemented in C. In order to evaluate the performance of the proposed NPU architecture a set of software products developed by KM211 company and the KMX32 family of microcontrollers were used. Evaluation of NPU performance was made on the basis of a simulation model. Estimates of the processing time of one packet and the average throughput of the NPU model for each scenario are obtained. |
topic |
network processor network processing unit switch computer networks sdn computer architecture simulation modeling open flow protocol |
url |
https://www.mais-journal.ru/jour/article/view/1161 |
work_keys_str_mv |
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