A Monolithic Three-Axis Accelerometer with Wafer-Level Package by CMOS MEMS Process - S. H. Tseng (Proceedings, 2017)
This paper presents a monolithic three-axis accelerometer with wafer-level package by CMOS MEMS process. The compositions of the microstructure are selected from CMOS layers in order to suppress the in-plane and out-of-plane bending deflection caused by the residual stresses in multiple layers. A switched-capacitor sensing circuit with a trimming mechanism is used to amplify the capacitive signal, and decrease the output dc offset voltage to ensure the desired output voltage swing. The CMOS MEMS wafer is capped with a silicon wafer using a polymer-based material. The measured sensitivities with and without a wafer-level package range from 113 mV/G to 124 mV/G for the in-plane (x-axis, y-axis) accelerometer, and from 50 mV/G to 53 mV/G for the z-axis accelerometer, respectively.