Tuning of SnS Thin Film Conductivity on Annealing in an Open Air Environment for Transistor Application - Thomas Daniel (East European Journal of Physics, 2020)
The study aimed at enhancement and optimisation of SnS conductivity via annealing for field effect transistor’s semiconductor channel layer application. Interstitials and vacancies in SnS films are known to cause carrier traps which limit charge carriers and hence limit the achievement of the threshold voltage for a field effect transistor operation. Tuning of SnS conductivity for transistor application is of emerging interest for novel device operation. SnS thin film semiconductors of 0.4  thickness were deposited using Aerosol assisted chemical vapour deposition and annealed in open air at annealing temperatures of150, 200, 250, 300 and 350 . Variation of the annealing temperature from 150 through 250  enhances the crystallinity of the annealed thin film samples by increasing the number of crystallites of the annealed films which is also buttress by the decreasing values of FWHM. However a further decrease in crystallite size at higher annealing temperature of 300 to 350  was observed which could be attributed to the fragmentation of clusters of crystallites at higher annealing temperature. Increase in annealing temperature increases grain size leading to the reduction in grain boundaries and potential barrier thereby changing the structure and phase of the films which in essence affects the electrical conductivity of the SnS thin films. The films annealed at 250 exhibited optimum conductivity. The average hall coefficients of the samples deposited at 150 to 250  were positive which indicates that the films annealed at this temperature range are of p type conduction while the average hall coefficients of the samples deposited at 300 and 350  were negative indicating that the films are of n type conduction. The conductivity change is essential for the use of SnS as a semiconductor channel layer especially in a field effect transistor where the device can be tuned to work as a p type or n type semiconductor channel layer.