0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process
We present a low voltage, low power operational transconductance amplifier (OTA) designed using a Fully Depleted Silicon-on-Insulator (FDSOI) process. For very low voltage application down to 0.5 V, two-stage miller-compensated OTAs with both p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) diffe...
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Online Access: | http://www.mdpi.com/2079-9268/2/2/155 |
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doaj-cf5e5be9864146df8d26731e24585ff22020-11-25T01:17:54ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682012-05-012215516710.3390/jlpea20201550.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) ProcessPiotr OlejarzKyoungchul ParkSamuel MacNaughtonMehmet R. DokmeciSameer SonkusaleWe present a low voltage, low power operational transconductance amplifier (OTA) designed using a Fully Depleted Silicon-on-Insulator (FDSOI) process. For very low voltage application down to 0.5 V, two-stage miller-compensated OTAs with both p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) differential input have been investigated in a FDSOI complementary metal oxide semiconductor (CMOS) 150 nm process, using 0.5 V threshold transistors. Both differential input OTAs have been designed to operate from the standard 1.5 V down to 0.5 V with appropriate trade-offs in gain and bandwidth. The NMOS input OTA has a simulated gain/3 dB-bandwidth/power metric of 9.6 dB/39.6 KHz/0.48 µW at 0.6 V and 46.6 dB/45.01 KHz/10.8 µW at 1.5 V. The PMOS input OTA has a simulated metric of 19.7 dB/18.3 KHz/0.42 µW at 0.4 V and 53 dB/1.4 KHz/1.6 µW at 1.5 V with a bias current of 125 nA. The fabricated OTAs have been tested and verified with unity-gain configuration down to a 0.5 V supply voltage. Comparison with bulk process, namely the IBM 180 nm node is provided and with relevant discussion on the use of FDSOI process for low voltage analog design.http://www.mdpi.com/2079-9268/2/2/155sub-thresholdweak inversionanalog designOTAlow powerFDSOI |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Piotr Olejarz Kyoungchul Park Samuel MacNaughton Mehmet R. Dokmeci Sameer Sonkusale |
spellingShingle |
Piotr Olejarz Kyoungchul Park Samuel MacNaughton Mehmet R. Dokmeci Sameer Sonkusale 0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process Journal of Low Power Electronics and Applications sub-threshold weak inversion analog design OTA low power FDSOI |
author_facet |
Piotr Olejarz Kyoungchul Park Samuel MacNaughton Mehmet R. Dokmeci Sameer Sonkusale |
author_sort |
Piotr Olejarz |
title |
0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process |
title_short |
0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process |
title_full |
0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process |
title_fullStr |
0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process |
title_full_unstemmed |
0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process |
title_sort |
0.5 µw sub-threshold operational transconductance amplifiers using 0.15 µm fully depleted silicon-on-insulator (fdsoi) process |
publisher |
MDPI AG |
series |
Journal of Low Power Electronics and Applications |
issn |
2079-9268 |
publishDate |
2012-05-01 |
description |
We present a low voltage, low power operational transconductance amplifier (OTA) designed using a Fully Depleted Silicon-on-Insulator (FDSOI) process. For very low voltage application down to 0.5 V, two-stage miller-compensated OTAs with both p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) differential input have been investigated in a FDSOI complementary metal oxide semiconductor (CMOS) 150 nm process, using 0.5 V threshold transistors. Both differential input OTAs have been designed to operate from the standard 1.5 V down to 0.5 V with appropriate trade-offs in gain and bandwidth. The NMOS input OTA has a simulated gain/3 dB-bandwidth/power metric of 9.6 dB/39.6 KHz/0.48 µW at 0.6 V and 46.6 dB/45.01 KHz/10.8 µW at 1.5 V. The PMOS input OTA has a simulated metric of 19.7 dB/18.3 KHz/0.42 µW at 0.4 V and 53 dB/1.4 KHz/1.6 µW at 1.5 V with a bias current of 125 nA. The fabricated OTAs have been tested and verified with unity-gain configuration down to a 0.5 V supply voltage. Comparison with bulk process, namely the IBM 180 nm node is provided and with relevant discussion on the use of FDSOI process for low voltage analog design. |
topic |
sub-threshold weak inversion analog design OTA low power FDSOI |
url |
http://www.mdpi.com/2079-9268/2/2/155 |
work_keys_str_mv |
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1725145080971395072 |