Enabling Variability-Aware Design-Technology Co-Optimization for Advanced Memory Technologies

Enabling Variability-Aware Design-Technology Co-Optimization for Advanced Memory Technologies

This paper presents a TCAD-based methodology to enable Design-Technology Co-Optimization (DTCO) of advanced semiconductor memories. After reviewing the DTCO approach to semiconductor devices scaling, we introduce a multi-stage simulation flow to study the device-to-circuit performance of advanced me...

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Bibliographic Details
Main Authors: Salvatore M. Amoroso, Plamen Asenov, Jaehyun Lee, Nara Kim, Ko-Hsin Lee, Yaohua Tan, Yong-Seog Oh, Lee Smith, Xi-Wei Lin, Victor Moroz
Format: Article
Language:English
Published: JommPublish 2020-12-01
Series:Journal of Microelectronic Manufacturing
Subjects:
dtco
statistical variability
process variability
semiconductor memories
dram
cmos
scaling
Online Access:http://www.jommpublish.org/p/60/

Internet

http://www.jommpublish.org/p/60/

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