Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures
Abstract We report the fabrication process and performance characterization of a fully integrated ferroelectric gate stack in a WSe2/SnSe2 Tunnel FETs (TFETs). The energy behavior of the gate stack during charging and discharging, together with the energy loss of a switching cycle and gate energy ef...
| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Nature Publishing Group
2021-09-01
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| Series: | npj 2D Materials and Applications |
| Online Access: | https://doi.org/10.1038/s41699-021-00257-6 |