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02079 am a22001693u 4500 |
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|a Abdul Tahrim, Aqilah
|e author
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|a Huei, Chaeng Chin
|e author
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|a Cheng, Siong Lim
|e author
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|a Loong, Michael Peng Tan
|e author
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|a Design and performance analysis of 1-Bit FinFET full adder cells for subthreshold region at 16 nm process technology
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|b Hindawi Publishing Corporation,
|c 2015.
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|z Get fulltext
|u http://eprints.utm.my/id/eprint/58228/1/AqilahAbdulTahrim2015_DesignandPerformanceAnalysisof1Bit.pdf
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|a The scaling process of the conventional 2D-planar metal-oxide semiconductor field-effect transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was invented to overcome the problem by allowing transistors to be scaled down into sub-20 nm region. In this work, the FinFET structure is implemented in 1-bit full adder transistors to investigate its performance and energy efficiency in the subthreshold region for cell designs of Complementary MOS (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate (TG), and Hybrid CMOS (HCMOS). The performance of 1-bit FinFET-based full adder in 16-nm technology is benchmarked against conventional MOSFET-based full adder. The Predictive Technology Model (PTM) and Berkeley Shortchannel IGFET Model-Common Multi-Gate (BSIM-CMG) 16 nm low power libraries are used. Propagation delay, average power dissipation, power-delay-product (PDP), and energy-delay-product (EDP) are analysed based on all four types of full adder cell designs of both FETs. The 1-bit FinFET-based full adder shows a great reduction in all four metric performances. A reduction in propagation delay, PDP, and EDP is evident in the 1-bit FinFET-based full adder of CPL, giving the best overall performance due to its high-speed performance and good current driving capabilities.
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|a en
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|a TK Electrical engineering. Electronics Nuclear engineering
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