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|a Agarwal, Anant
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|a Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
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|a Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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|a Agarwal, Anant
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|a Agarwal, Anant
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|a The Other Face of On-Chip Interconnect
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|b Institute of Electrical and Electronics Engineers,
|c 2010-04-27T16:32:15Z.
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|z Get fulltext
|u http://hdl.handle.net/1721.1/54237
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|a The multicore revolution has changed the way we think about computing. The same movement has also changed the way we look at on-chip interconnect because it is a key determinant of the performance and power efficiency of multicores. This talk will highlight some of the lesser known issues and opportunities of on-chip interconnect, such as protection, programming ease, and the impact on the basic structure of our software. The talk will borrow heavily from our experiences with on-chip interconnect in university research with the 16-core Raw multicore processor, in a commercial environment with Tilera's 64-core Tile processor, and in a future 1K-core multicore processor called ATAC that integrates optical and electrical interconnects.
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|t Proceedings of the 17th IEEE Symposium on High Performance Interconnects, 2009. HOTI 2009.
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