ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores

• Main Authors: Khan, Omer (Contributor), Hoffmann, Henry Christian (Contributor), Lis, Mieszko (Contributor), Hijaz, Farrukh (Author), Agarwal, Anant (Contributor), Devadas, Srinivas (Contributor)
• Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science (Contributor)
• Format: Article
• Language: English
• Published: Institute of Electrical and Electronics Engineers, 2012-06-28T20:01:54Z.
• Subjects: Article
• Online Access: Get fulltext

This paper proposes an architecturally redundant cache-coherence architecture (ARCc) that combines the directory and shared-NUCA based coherence protocols to improve performance, energy and dependability. Both coherence mechanisms co-exist in the hardware and ARCc enables seamless transition between the two protocols. We present an online analytical model implemented in the hardware that predicts performance and triggers a transition between the two coherence protocols at application-level granularity. The ARCc architecture delivers up to 1.6× higher performance and up to 1.5× lower energy consumption compared to the directory-based counterpart. It does so by identifying applications which benefit from the large shared cache capacity of shared-NUCA because of lower off-chip accesses, or where remote-cache word accesses are efficient.
United States. Defense Advanced Research Projects Agency (DARPA UHPC Program)