Full utilization, fairness, and access delay on high speed slotted bus networks

Full utilization, fairness, and access delay on high speed slotted bus networks

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997. === Includes bibliographical references (p. 89-92). === Supported by the U.S. Army Research Office. ARO ASSERT DAAH04-94-G-0221 Supported by National Science Foundation. NCR-92036379 S...

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Bibliographic Details
Main Author: Chiu, Angela Lan
Other Authors: Massachusetts Institute of Technology. Laboratory for Information and Decision Systems.
Format: Others
Language:English
Published: Massachusetts Institute of Technology, Laboratory for Information and Decision Systems 2005
Subjects:
Laboratory for Information and Decision Systems.
TK7855.M41 E3845 no.2382
Online Access:http://hdl.handle.net/1721.1/10699

Internet

http://hdl.handle.net/1721.1/10699

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