Design of a Mixed Signal Analog-Digital Simulator for CMOS VLSI Circuits

• Main Authors: Jony Shiang Lin Bie, 白祥麟
• Other Authors: Steve S.Chung
• Format: Others
• Language: en_US
• Published: 1993
• Online Access: http://ndltd.ncl.edu.tw/handle/63874370076687970747

碩士 === 國立交通大學 === 電子研究所 === 81 === The mixed-mode simulator is currently one of the most efficit tools for timing verification of analog-digital CMOS VLSI circuits. We have developed a mixed-mode simulator by combining the conventional circuit level simulation techniques, sampled- data level circuit techniques for analog circuit simulation and the gate level techniques for digital circuit simulation based on the event-driven concept. A new scheme at the macrocell level is proposed for memory storage savings and less execution time required while preserving reasonable accuracy. It decomposes a circuit into a number of subcircuits called macrocells. The scheme can exploit a general multirate behavior that refers to macrocell simulation at different rates over a given interval of time so that different algorithms can be employed in the simulator. Furthermore, a new partitioning scheme called block tearing approach is proposed, in which timing partition is used in addition to the partition of macrocells. It can further be implemented in multi-processor machines to speed up since these partitioned blocks are built upon the pipeline structure. Benchmark tests of several example circuits show good performance in terms of speed and accuracy. The simulator is well suited for hierarchical VLSI circuits which are cell- based such as current circuit design.