The design of a concurrent video signal processor
碩士 === 國立交通大學 === 電子研究所 === 82 === In this thesis, a video signal processor(VSP) with a concurrent architecture is proposed. This architecture consists of three independent processing units: the arithmetic unit(AU), the multiplier unit(MU)...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1994
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| Online Access: | http://ndltd.ncl.edu.tw/handle/85133873227247679687 |