A 10-bit 60MHz pipelined CMOS analog to digital converter
碩士 === 國立成功大學 === 電機工程研究所 === 83 === In this thesis, we design a single 5-V, 10-bit 62.5MHz pipelined CMOS analog-to-digital converter ADC) for video-rate signal processing. This conversion is the fastest of published pipeline CMOS ADCs up to now. In our...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1995
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| Online Access: | http://ndltd.ncl.edu.tw/handle/50837276096679760824 |