Analysis and Design of CMOS Analog-to-Digital Converter

• Main Authors: Jin-Cheng Huang, 黃金城
• Other Authors: Chung-Yu Wu
• Format: Others
• Language: en_US
• Published: 1995
• Online Access: http://ndltd.ncl.edu.tw/handle/82435285176569206390

碩士 === 國立交通大學 === 電子研究所 === 83 === In this thesis, an 8-bit 62.5MS/sec A/D converter designed and fabricated in a 0.8um CMOS process, is presented. The A/D converter was designed to have a sampling time of 8ns(including the nonoverlapping time with 2ns) at clock rate of 125MHz. The 8-bit 12.5MS/sec A/D converter cell is implemented by a four- stage architecture. This structure can be designed without the operational amplifiers with either high gain or a large output swing. The parallel processing is applied to the five A/D converters connected in parallel to improve the conversion rate up to five times speed. The linearity error is within 1/2 LSB. The post-simulation result shows the throughout rate can be 12.5MS/sec with 8-bit resolution for the A/D converter cell. The core of the 62.5MS/sec parallel A/D converter array occupies an area of 3.2mm×4.6mm, and the power consumption is about 150mW.