Timing Recovery Architecture for CAP-based ADSL Transceiver and VCO VLSI Design
碩士 === 國立中央大學 === 電機工程研究所 === 83 === A mixed analog-digital dual loop hybrid phase-locked loop (DHPLL) architecture for CAP-based (Carrierless Amplitude/Phase Modulation) ADSL-1 (Asymmetric Digital Subscriber Line) system is proposed. Key...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1995
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| Online Access: | http://ndltd.ncl.edu.tw/handle/69799379321385997114 |