| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 83 === In this thesis, we will present syndrome test for partially
scanned MCM. We will do a detail mathematical analysis of
syndro me testing. There are two issues in syndrome testing,
one is tes t hardware structure another is to determine the
test patterns a nd test length. According to the two issues, We
will develope a n algorithm to determine weight, test length,
and observation po ints. We will also design a hardware
structure for the BIST of partially scanned interconnects based
on the results of the anal ysis. Finally, to verify the
hardware structure we run Verilog simulation in two test cases,
a fault-free case and a faulty cas e.
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