A Gate-Level Schematic Generation System and Its Applications on Circuit Testing
碩士 === 國立成功大學 === 電機工程研究所 === 84 === In this thesis, an Automatic Gate-level Schematic Diagram generation system called AGSD is developed. We divide the schematic generation work into seven phases: level assignment , virtual module insertio...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1996
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| Online Access: | http://ndltd.ncl.edu.tw/handle/67276009218211633831 |