| Summary: | 碩士 === 國立中興大學 === 資訊科學學系 === 86 === The increase in integration capacity as well as new packaging
techniques creates new possibilities. Multi-chip modules
have been in use for some times, and single- chip systems
for some simple applications have been successfully built.
Despite the similarity between PCBs (printed circuit boards)
and core-based chips in system architecture, it is
difficult to apply board-level testing technique to the single-
chip environment.
A core supplier may be not willing to give any information about
the internal logic of cores. As a result, applicable
the traditional test generation process such as ATPG (Automatic
Test Pattern Generation) and fault simulation is not performed.
However, the core vendor usually specifies the set of test
vectors that must be applied to the core to guarantee sufficient
fault coverage. Testing
embedded cores is a difficult because access to core I/O is
limited. The UDL (user-defined logic) surrounding the
core may restrict the set of test vectors that can be applied to
the core. Some of the core testing vectors may not be contained
in the output space of the UDL that drives the core and
cannot be justified at the core inputs.
This paper present an approach to insert control points in the
UDL to modify its output space so that it contains the
specified core testing vectors. It eliminates the need for an
isolation ring and its associated multiplexor delays.
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