Teslog: An Interactive Schematic Generation System for Logic Design and Testing

• Main Authors: Lee, Geeng-Wei, 李耿維
• Other Authors: Kuen-Jong Lee
• Format: Others
• Language: zh-TW
• Online Access: http://ndltd.ncl.edu.tw/handle/11242912214517011193

碩士 === 國立成功大學 === 電機工程學系 === 86 === An interactive schematic generation system for logic design and testing, namedTeslog, is presented in this thesis. It is inherited from the previousdeveloped systems, AGSD and AGSS, and reconstructed with C++ language on PCsystems. Teslog owns the ability of schematic generation, real-time circuit statusdisplay, testing analysis for both combinational and sequential circuits, andprovides an interface for program interaction. It offers testing applicationsof logic simulation, fault simulation, test generation, and critical pathanalysis for combinational circuits, and provides logic simulation forsequential circuits. In summary, Teslog can generate schematic for a circuit and real-time displaythe variation of circuit status on screen while circuit analysis methods areapplied to the circuit. Besides, by the program interface embedded in Teslog,programmers can utilize its schematic generator and functions in their ownprograms and facilitate their work on circuit analysis.