The Analysis and Design of a 10-Bit Three Stages Pipelined Analog-to-Digital Converter
碩士 === 國立海洋大學 === 電機工程學系 === 86 === In this thesis, we design a 10-bit, 20MSamples/s, three stagespipelined CMOS analog-to-digital converter (ADC). The framework contains three 4-bit stages. The main subcircuits of the ADC are sample/hold circuit, 4-bit f...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1998
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| Online Access: | http://ndltd.ncl.edu.tw/handle/47755008262309895361 |