| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 87 === It is well known that scaling down both the supply voltage and threshold voltage is effective in reducing the power consumption while maintaining the high operation speed. However, it induces some problems, for instance, the standby power is increased dramatically. In order to cope with the problem, several circuit schemes are proposed. We classify those schemes into 3 classes: 1) Multiple Threshold voltage(MTCMOS) 2) Variable Threshold voltage with substrate bias controlling (VTCMOS) 3) combined MTCMOS and VTCMOS(MVCMOS). In addition, Silicon on Insulator (SOI) based technology is also discussed.
In this thesis, we also proposed an improved RCSFF (Reduced Clock Swing Flip-Flop) circuit design which is applicable to both active and standby mode. The improved flip-flop is made of low-Vth devices to achieve high speed with serial cut-off high Vth MOSs. 6T SRAM cell is added to the flip-flop to hold the latched data in the standby mode. The 6T SRAM storage element is composed of high-Vth MOSs to suppress leakage current in standby mode.
Finally, we adopted the improved RCSFF(Reduced Clock Swing Flip-Flop) circuit to design parallel, low power, high speed, and 2-stage pipelined multipliers with Modified Booth algorithm. From the architecture design, circuit design to floor plan and routing, high speed and low power consumption are our design guidelines. 16*16 bits and 32*32 bits multipliers are implemented to demonstrate the effectiveness of our techniques. From our simulation results, the low power consumption and high operation speed do achieve our expectation.
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