An Application of TOC for Photolithography Area in Wafer Fabrication Factory

• Main Authors: Yu-Chen Lin, 林玉貞
• Other Authors: Rong-Kwei Li
• Format: Others
• Language: zh-TW
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/31363041061571903926

碩士 === 國立交通大學 === 工業工程與管理系 === 88 === In manufacturing line of IC , the structure of device to be made on wafer through repeat processes. All of wafers should be defined patterns at photo process and then delivered to next operational step for processing based on process flow. From manufacturing point of view, photo area would be assigned as a controlling center among wafer processes inside fab. But photo area is always become a bottleneck of manufacturing line because stepper with the highest equipment cost. By the way, fab operation is always suffers from mutual impact between priority of fabrication equipment in order to meet both the maximum throughput and on time delivery simultaneously. So, how to elevate the throughput of steppers and reduce WIP at bottleneck are the key tasks of fab operation. In other words, it’s a key topic to get the top performance of bottleneck or steppers in order to gain the maximum throughput of fab. This study plan to develop a optimal system to do both the proper wafer input and the best drum of WIP at the bottleneck in order to get the maximum output of wafer fab based on drum-buffer-rope production management technology. By the way, this study also try to reduce the mutual impact of production management and target to get balance between on time delivery and the maximum output through both the optimal rope and performance management. In other words, the full utilization of bottleneck and the order performance of non-bottleneck would be emphasized. The confirmation of the optimal system of this study is done in M-company for wafer input and dispatching operation inside fab. Before confirming, the parameter of wafer input is established through calculation of bottleneck’s loading such as stepper’s reasonable weight and warning level based on the distribution of processing wafer in manufacturing line. During the operational confirmation, M-company’s WIP, capacity of equipment and process flow of running products are used for both wafer input and dispatching operation through some running systems or software like workstream, SQL and Delphi. The results of confirmation showed the better performance compared with the original operation regarding the throughput of bottleneck, the cycle time of product, WIP level inside fab. 中文摘要 英文摘要 目錄 圖目錄 表目錄 第一章 緒論……………………………………………………… 1-1研究背景……………………………………………… 1-2研究目的……………………………………………… 1-3研究範圍……………………………………………… 1-4研究步驟……………………………………………… 第二章 晶圓廠投料及派工法則的構建……………………… 2-1晶圓廠投料及派工法則的構建…………………… 2-1-1黃光區生產作業流程………………………… 2-1-2 機台特性……………………………………… 2-2 派工方法的改善…………………………………… 2-3 投料模式構建………………………………………. 2-4 修正績效指標………………………………………. 第三章 實例驗證……………………………………………… 3-1 M公司的驗證前的生產控制模式………………… 3-2生產環境資料………………………………………. 3-3實例執行過程………………………………………. 3-4模擬結果與分析……………………………………. 第四章 結論與未來研究方向…………………………………. 4.1結論…………………………………………………. 4.2未來研究方向………………………………………… 參考文獻………………………………………………………….. 附錄1 附錄2 附錄3 附錄4