The Analysis and Design of Split-Path Readout CMOS Active Pixel Sensor Circuits

• Main Authors: Yung-Kuo Ho, 何勇國
• Other Authors: Hwang-Cherng Chow
• Format: Others
• Language: zh-TW
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/99973386116265923832

碩士 === 長庚大學 === 半導體研究所 === 89 === In recent years, CMOS image sensors have been extensively noticed and applied. The major reason is that customers popularly and continuously notice the demand for low-power, low-cost and light-thin-short-small feature of products. In additions, there is another advantage for CMOS image sensors that they can integrate distinct systems of VLSI electronics on a single chip and reduce packaging costs, and as being operated with single and standard supply voltage, the power consumption of this kind of camera-on-a-chip system may be measured in the tens of milli watts. In this thesis, we propose an improved CMOS image sensor structure. On the active pixel design, we use the manner of pixel-shared split-path readout to reduce the complexity of each pixel to only two transistors. Due to the reduction of the transistor count, the size of each pixel is 8×8μm2 and the fill factor can be increased to 49% to enhance the quantum efficiency. By the N-well/P-sub structure taken as the photodiode, the sensor will get both smoother photon-electron current and wider sensing range of different wavelengths. To reduce the fixed pattern noise (FPN), the delta-differential sampling circuit is used for the photo signal readout. A 128×128 CMOS image sensor including pixel sensor array, decoder, and readout amplifier circuit are designed based on TSMC 0.35μm 1P4M CMOS technology. Judging from the simulation results, the power consumption is 52mW for a single 128 pixel-array at 3.3V power supply, and the frame readout rate reaches 300 frames per second.