| Summary: | 碩士 === 國立交通大學 === 材料科學與工程系 === 89 === As interconnect features size shrink down to deep sub-micron region, and the overall chip speed would be limited mainly to the on-chip interconnect RC delay, not to that of device gate RC delay, and copper interconnect have been recognized as the promising mainstream for its application on high performance, and reliability for ultra-large scale integration (ULSI) semiconductor manufacturing. The current main-stream of copper metallization method is carried out by blanket Cu electroplating deposition capable of gap-filling into high-aspect-ratio vias and trenches, and implement of multi-step Cu chemical mechanical polishing (CMP) to remove the overburden Cu and TaN barrier outside of features, known as the Damascene or metal-inlaid process. The multi-step Cu CMP to precisely remove copper and tantalum or titanium nitride barrier outside the trenches without Cu over-polish would be difficult owing to the unequal removal selectivity. On the other hand, regarding the increasing aspect ratio of wires and vias, conventional physical vapor deposition (PVD) Cu seeding for the following Cu electroplating would face the step-coverage limit beyond 0.10 μm tech-node due to the poor sidewall and bottom corners coverage or overhanging on the top corners. Although the chemical vapor deposition (CVD) or electroless Cu seeding could benefit from excellent step coverage, but Cu seed formed by CVD method would suffer from the carbon or nitrogen impurities decomposed from of the metallic-organic precursors and rough surface
In our study, we proposed a novel selective Cu metallization process by electrochemical contact displacement, instead of the troublesome Cu seeding and electroplating, and the complicated multi-step CMP process. Implement of the intrinsically selective Cu contact displacement from amorphous Si and the relative simple Si CMP to remove the overburden Si outside of the trenches, the selective Cu metallization can be carried out. The quality of deposited Cu film, like the electrical resistance, crystal grain orientation, adhesion to the underlying Ta barrier layer, would be evaluated by means of sheet resistance, X-ray diffraction, and stud pull testing.
In addition, a novel selective galvanic deposition of Cu seed directly on the Ta barrier is also evaluated in this work. It would benefit from not only the good gap-filling capability but also the intrinsic selective deposition on the Ta barrier. In order to selectively forming Cu seed within the trenches, Ta barrier outside of trenches would be removed by CMP. After Cu seed formation, electroless plating using alkaline formaldehyde chemistry could be carried out to selectively depositing Cu into trenches. By means of this approach, both of the step-coverage issues of Cu seeding and complicated multi-step Cu CMP could be overcome.
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