A novel All Digital Phase Locked Loop (ADPLL) with ultra fast frequency lock and high oscillation frequency
碩士 === 淡江大學 === 電機工程學系 === 89 === This thesis proposed a novel architecture for All Digital Phase-Locked Loop . As we know that a PLL-based circuit has been widely used in many applications such as frequency synthesizer , data recovery circuit , and delay de-skewing . Above circuits are u...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/18014911762767217144 |