Implementation of Combing the Implementation of Combing the Data Reuse

• Main Authors: Der Shan Tzeng, 曾德山
• Other Authors: Jong-Jiann Shieh
• Format: Others
• Language: en_US
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/90742706473707457808

碩士 === 大同大學 === 資訊工程研究所 === 89 === We present a new approach for improving the parallelism that advanced computer architectures exploit at run-time from a sequential program (e.g. Superscalar processors). The new approach termed speculation value reuse mainly suggests to predict source operands of instructions and to supply the predicted values to reuse buffer to obtain speculative result. As a result, the processor can speculatively execute the true-data dependent instructions in parallel and extract Instruction-level parallelism beyond the limits of the program's dataflow graph. The capability to use this new technique is based on new observations on the nature of computer programs. There is significant result redundancy in programs. In other words, many instructions perform the same computation and, hence, produce the same result over and over again. Some studies have found that, for several benchmarks more than 75% of the dynamic instructions produce the same result as before. We propose an new method that produce speculative result by combining the advantage of VP and VR that can increase predictable rate and improve ILP. In addition, we also apply a reissue mechanism for our dataflow speculation execution micro-architecture to obtain more benefit.