The Study of Ultra-Thin Nitride-Related Gate Dielectrics for Deep Sub-Micron CMOS Process Application
博士 === 國立成功大學 === 電機工程學系碩博士班 === 90 === As the aggressive downscaling of CMOS technology continues, further reduction of gate oxide thickness is essential for low supply voltage and high driving capability. However, the excessive gate direct tunneling and the boron penetration issues phase out the u...
Main Authors: | Chien-Hao Chen, 陳建豪 |
---|---|
Other Authors: | Mong-Song Liang |
Format: | Others |
Language: | en_US |
Published: |
2002
|
Online Access: | http://ndltd.ncl.edu.tw/handle/b5zf9z |
Similar Items
-
Study on deep sub-micron mosfets with ultra thin silicon nitride gate dielectric
by: Yu Chun Tang, et al.
Published: (2003) -
Advanced Deep Sub-Micron MOSFETs with Ultra-Thin High-k Gate Dielectrics and Strained SiGe Channel
by: Ching-Wei Chen, et al.
Published: (2005) -
A Study of Ultra-thin Gate Oxides on Deep Sub-micron Devices
by: Hsien, Szu-Kang, et al.
Published: (1997) -
Study on Hot Carrier Degradation in Deep Sub-Micron Nitride Spacer and Ultra-Thin oxide
by: Chun-Lin Tsai, et al.
Published: (2002) -
The Impact of Boron Penetration on Deep Sub-micron Dual-gate CMOS
by: Kuan Miao Liu, et al.
Published: (1999)