Implementation of JPEG Multimedia System with Hardware/Software Co-design on SOC Development Platform

• Main Authors: Chin-Jen Yang, 楊智仁
• Other Authors: Bin-Da Liu
• Format: Others
• Language: zh-TW
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/65xqxs

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 90 === In this thesis, a JPEG multimedia system following the hardware/software co-design and co-verification principle is implemented on SOC development platform which includes ARM7TDMI microprocessor and chipset. From the analysis of computational JPEG system, DCT and VLC are highly repetitive and occupy 51% in the total computation. Therefore, we implemented DCT and VLC functions in hardware.The hardware of DCT is implemented in recursive architecture and VLC is in pipelined architecture. Concerning the integration of JPEG system, we design a wrapper to serve as the communicational interface between the proposed chip and AHB bus. Then we apply RAM-based interface to communicate ARM7TDMI with the designed chip. Thus in this design, our chip plays a slave role, and ARM7TDMI plays a master role which is responsible for complex controls and data access. When JPEG programs run to DCT or * The author ** The Advisors VLC function, ARM7TDMI stores data into the local memory within designed chip. After a fixed numbers of cycles, ARM7TDMI reads out computed data from the chip and continue to execute the next functions in programs. ARM7TDMI will proceed the above actions until JPEG programs are finished. In the final verification, the system has successfully compressed quite a few pictures, and these compressed pictures are able to be decompressed accurately and correctly by general JPEG decompression programs. The maximum frequency at which integrated hardware can be operated on FPGA is 22.364MHz, and the number of gate counts is 135K.