Fabrication and Characterization of SOI FinFETs with Schottky Barrier Source/Drain

• Main Authors: Fu Ju Hou, 侯福居
• Other Authors: Tiao Yuan Huang
• Format: Others
• Language: zh-TW
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/05591667974984877700

碩士 === 國立交通大學 === 電資學院學程碩士班 === 90 === In this thesis, we proposed and demonstrated a novel nano-scale silicon-on-insulator (SOI) FinFET device. The new device features a metallic silicided source/drain and field-induced S/D extensions. For the device fabrication, the patterning of nano-scale Si lines using electron-beam lithography with NEB-22 or hydrogen silsesquioxane (HSQ) resist was examined firstly. Since the HSQ resist has the advantages of high contrast and less line width fluctuation up to 1nm, the sub-50nm silicon lines can be more easily achieved. Nevertheless, the required high dosage up to several hundreds µC/cm2 and the severe proximity problem make the HSQ unlikely to be used in practical applications. Therefore, NEB-22 e-beam resist, with its potentially higher commercial applicability in the future, was chosen in this work to generate sub-50nm silicon fin patterns. Concomitantly, high etch selectivity between silicon and the underlying silicon dioxide is essential to the nano-scale device fabrication, owing to the use of ultra-thin gate oxide. To overcome this issue, an advanced TCP-9400 poly-Si etcher was employed. An excellent recipe having high etching ratio (up to 200) as well as anisotropic etched profile was successfully developed in this work. Schottky barrier (SB) MOSFETs generally enjoy simpler and low-temperature processing compared to conventional MOS transistors by employing metallic silicide, in lieu of heavily-doped region, as the source/drain. However, conventional Schottky barrier (SB) MOSFETs were known to suffer from intolerantly high leakage current caused by the field emission of carriers from the drain junction. The high leakage severely degrades the on-/off-state current ratio and essentially rules out their applications to mainstream integrated circuits. In our new device, this problem was effectively solved by the formation of an electrical drain junction which was induced by the sub-gate bias, VG,sub. Our results show, for the first time, that the new device with Co-silicide source/drain exhibits superior ambipolar characteristics by simply switching the bias polarity on the main-gate and the sub-gate bias. Excellent subthreshold characteristics with high on-/off-state current ratio (close to or higher than 109) and near-ideal subthreshold slope (~ 60 mV/decade) are realized, for the first time, on a single device. Moreover, we show that the new device with Pt-silicided source/drain can further improve the p-channel drivability and transconductance, albeit compromising the capability of bi-channel operation, due to its low barrier height for holes (Φbop = 0.24 V) and a high barrier height for electrons (Φbon = 0.86 V).