Study of BEOL Process Induced High Resistance in IC's Manufacturing
碩士 === 國立交通大學 === 電資學院學程碩士班 === 90 === Abstract In this thesis, there are two topics of BEOL (Back End of Layers) process to be studied. One is the study of process-induced high via contact resistance problem. The other is the study of process-induced abnormal interconnection...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/25238311042160198401 |