Scalable Communication Processor
碩士 === 國立臺灣大學 === 電信工程學研究所 === 90 === In this thesis, the design of a scalable communication processor is presented. Four modes are defined in the processor to provide the scalability, including 802.11a OFDM receiver, 802.11b DSSS/PBCC receiver, DAB receiv...
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/23496061394642409365 |
| Summary: | 碩士 === 國立臺灣大學 === 電信工程學研究所 === 90 === In this thesis, the design of a scalable communication processor
is presented. Four modes are defined in the processor to provide
the scalability, including 802.11a OFDM receiver, 802.11b
DSSS/PBCC receiver, DAB receiver and DVB receiver. The functions
and computation complexity in the four modes will be analyzed to
group into three hardware blocks. The categorization of the
operations reduces the whole hardware complexity by reusing the
hardware blocks.
The OFDM receiver design and the DSSS/PBCC receiver design are
both proposed in this thesis. In addition, the functional and
fixed-point simulation are performed to verify the proposed
architecture. The proposed communication processor retains both
the flexibility in software design and the computation capability
in hardware.
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