Design and Implementation of Multi-Stage Delta-Sigma Modulators
碩士 === 國立臺灣科技大學 === 電子工程系 === 90 === Oversampled analog-to-digital converters based on delta-sigma ( ) modulation are attractive for VLSI implementation because they are especially tolerant of circuit nonidealities and component mismatch. This thesis presents the design and implementation of a 4th o...
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| Format: | Others |
| Language: | zh-TW |
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2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/25746314038468982714 |
| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 90 === Oversampled analog-to-digital converters based on delta-sigma ( ) modulation are attractive for VLSI implementation because they are especially tolerant of circuit nonidealities and component mismatch. This thesis presents the design and implementation of a 4th order cascade of lowpass and bandpass multi-stage noise shaping (MASH) modulators. The modulator components include the discrete-time integrator, the 1-bit quantizer, and the clock generator. We employ correlated double sampling (CDS) in the integrator to suppress flicker noise, thermal noise and offset voltages. The operational amplifier of the integrator has very high dc gain in order to suppress leakage quantization noise.
Experimental results are presented for a 0.35um CMOS implementation. The experimental prototype modulator achieves a pick signal-to-noise plus distortion ratio (SNDR) of 71dB at a clock rate of 0.8MHz for a 25-kHz signal bandwidth (OSR=16). The noise floor has been suppressed about 80dB below the peak fundamental signal.
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