Advanced Scan Architecture for Test Time and Test Volume Reductions
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === Scan-based techniques are the most commonly used design for test (DFT) techniques for large digital circuits. However, long test time and large amount of test volume are two serious problems in a scan-based design. The above two problems will result in more de...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/92263566111501235004 |