Congestion-Driven Floorplanning

• Main Authors: Chung-Chiao Chang, 張仲喬
• Other Authors: Tsai-Ming Hsieh
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/57yyd3

碩士 === 中原大學 === 資訊工程研究所 === 92 === Floorplanning plays an important role in physical design of VLSI circuits. It plans the shapes and locations of the modules on the chip, and the result of which will greatly affect the performance of the final circuit. As technology continues to scale down, the number of transistors and interconnections increasing rapidly, chip performance degradation caused by interconnection becomes more and more obvious. Therefore the related problems for interconnection optimization have been processed as early as possible in physical design of VLSI circuits design flow. Area minimization becomes less important while the minimization of interconnection length, the reduction on congestion, and the satisfaction at delay constraints become the major concern in floorplanning. In this study, we analyze the distribution of wire congestion in a floorplan and propose the wire congestion model in response to the optimization problem relating to congestion in a floorplan. The advantages of our new model are listed as follows: (1) The results of the estimated wire congestion in soft module floorplanning by the model is more accurate than those determining position of the I/O pins by intersection-to-intersection method. (2) Different from the probability analysis based congestion model with fixed-size estimating grid, the new model has no shortcoming in how to determine the size of the grid. (3) Time complexity of the new model is O(n^2), where n is the number of modules, such that the time used in estimating the wire congestion is effectively reduced. Furthermore, combining the concept of reshaping and sizing of modules and the new congestion model, the nonlinear mathematical programming model is formulated to solve the congestion minimization problem according to the distribution of wire congestion. We test our new congestion model and mathematical programming based floorplanning algorithm with module partition by three experimental methods: (1) We implement three floorplanning algorithms: embedded the new congestion model; without considering congestion; probability analysis based congestion model with fixed-size estimating grid. Experimental results show that our new model improves the floorplan solution on congestion. (2) We compare our new model with the probabilistic model with different size of fixed-size grid. Experimental results show that congestion can be better optimized using the new model with little penalty in area and wirelength. (3) Furthermore, by partitioning the module based on mathematical programming, we can obviously reduce the congestion of a given floorplan.