| Summary: | 碩士 === 逢甲大學 === 電子工程所 === 92 === High performance CMOS analog-to-digital converters (ADC’s) are key components of mixed-signal integrated circuits. Recent applications of ADC are increasing in digital data reading fields, such as hard disk drives, digital videodiscs, and local-area networks. In all of these applications, high sampling speed is required, however resolution as low as 6-bit is sufficient. In the thesis, a new 6-bit 500 MS/s analog-to-digital converter (ADC) is proposed for high-speed and low-power CMOS integrated systems. This design is based on a proposed thermometer-code to gray-code encoder that not only reduces the power consumption and hardware cost of ADC converter, but also improves circuit performance. The simulation results indicate that this ADC works up to 500 MS/s with power consumption less than 43 mW at 3.3 V. The ADC occupies only 0.82 mm2 with the TSMC 0.35 μm single ploy quadruple metal (SPQM) CMOS technology. This design is suitable for standard CMOS technology with high-speed and low-power VLSI implementation. It is well applied when embedded into system-on-chip (SoC) circuit designs.
|
|---|
