A Study to grade of against Electronic Static Discharge for Wafer Packaging Industry

碩士 === 國立高雄第一科技大學 === 環境與安全衛生工程所 === 92 === The electronic products have been changed day by day, month by month; therefore, time is one of the most significant factors to make the profits in electronic market. For instance, Great Britain Dell issued the latest central processing unit (CPU) much ear...

Full description

Bibliographic Details
Main Authors: Jong-Ren Chen, 陳忠仁
Other Authors: Hong-Te Hsu
Format: Others
Language:zh-TW
Published: 2004
Online Access:http://ndltd.ncl.edu.tw/handle/04664383457215983315
Description
Summary:碩士 === 國立高雄第一科技大學 === 環境與安全衛生工程所 === 92 === The electronic products have been changed day by day, month by month; therefore, time is one of the most significant factors to make the profits in electronic market. For instance, Great Britain Dell issued the latest central processing unit (CPU) much earlier than his competitors over three months. During the initial stage of product cycle time, Intel sets up the higher price for getting better profits. After his competitor such as AMD or VIA entered this market, Intel may lower the price in order to share bigger market portion. This kind of strategy makes Intel a leading role in CPU market. Furthermore, the manufacturers of electronic products should shorten the product cycle time such as design, research and develop (R&D), manufacture, advertise, and promote. These processes should be considered during the same period, so those should be arranged more efficiency. While company manufactures a new product, the engineers should consider the difficulties of design and R&D processes in advance. For example, the Integrate Circuit (IC) designer should focus on the IC function and Wafer Packing company may solve the problems of ESD destroy. Thus, suitable arrangement could shorten the product cycle time. Currently, our semiconductor packaging industry does not have its own brand names such as Advanced Semiconductor Engineer (ASE), OSE…etc. Customers are located in worldwide and the requirements of ESD level were various by each customer. Semiconductor Packaging Industry should invest best equipment in order to reach the requirement of various customers. This research is based on a new system how to estimate the ESD level before the packaging process.This system could distinguish the various stages of ESD from various customers. The crucial part of this system will provide customers to recognize the defect of product if the defect was caused by IC designer. This research introduces this system if it works before packing process to customers. As a result, sampling the ESD stage before packing process will increase the yield of products. Customers could get better profits if they submit this system which could anti-ESD. There will be a comparison between two processes that one is testing the ESD before packaging process, and the other is testing after packaging process. If there is no big difference between these two processes. In conclusion, the ESD testing equipment could be setup in standard operation process (SOP).