Design and Implementation of Low Power Turbo Code Decoder

• Main Authors: Sung-han Wu, 吳松翰
• Other Authors: Yun-nan Chang
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/17990388696162978770

碩士 === 國立中山大學 === 資訊工程學系研究所 === 92 === Design of low power Turbo decoder is one of the key issues in many modern communication systems such as 3 GPP. For the Turbo decoder architecture, the memory for the storage of the branch metric and state metric represents a major part of the entire decoder no matter in silicon area or power dissipation. Therefore, instead of saving the computed branch memory, this thesis adopts an alternative approach by saving the input in order to generate the branch memory on line. Furthermore, a novel design of state metric unit is proposed such that the size of the total state metric can be effectively reduced by a half with slightly overhead of adders/subtractors. For non-recursive systematic encoding applications, the same design methodology can further reduce the number of arithmetic units required in the soft-output calculating module. Our preliminary experimental result shows that the proposed design methodology can achieve 40% and 13% reduction on the gate count and power dissipation respectively.