The Optimal TestRail Architecture for Core-Based SOC testing
碩士 === 淡江大學 === 電機工程學系 === 92 === Because of the great improvement of VLSI technology in recent years, the number of transistors on a sole chip become more and more, and the area of chip actually are smaller and smaller. It causes a tendency to design a system on a chip (SOC). The SOC contain wirele...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/22497859436071458211 |