| Summary: | 碩士 === 國立雲林科技大學 === 電子與資訊工程研究所碩士班 === 92 === Many of the applications nowadays utilize the digital signal processing (DSP) to resolve the transmitted information. Therefore, an analog to digital interface is required between the received analog signal and the DSP system. With the explosive growth of wireless communication systems and portable consumer electronics, the demand for low-power integrated circuits is indispensable. In many types of CMOS analog to digital converter (ADC) architectures, a pipelined architecture can achieve good dynamic range performances and the same throughput as the flash ADC due to the pipelined operation in each stage. This thesis focuses on the high-speed design of pipelined ADC. In the meanwhile, we try to minimize the power dissipation as well.
In this thesis, a 10-bit 50MHz pipelined A/D converter, with 1.5-bit resolution per stage, has been succeddfully designed and implemented using the TSMC 0.25μm CMOS process. Simulation results show that the designed pipelined ADC can operate at 50MHz with 58.26dB signal-to-(noise+distortion) ration - conforming to the 10-bit accuracy, and the estimated power dissipation is about 136.8 mW. Total layout area is about 1050×845um2.
|
|---|
