10-bit 50MHz Sampling Rate CMOS Pipelined Analog-to-Digital Converter
碩士 === 國立雲林科技大學 === 電子與資訊工程研究所碩士班 === 92 === Many of the applications nowadays utilize the digital signal processing (DSP) to resolve the transmitted information. Therefore, an analog to digital interface is required between the received analog signal and the DSP system. With the explosive growth of...
Main Authors: | Yu-Yun Huang, 黃于芸 |
---|---|
Other Authors: | Ming-Hwa Sheu |
Format: | Others |
Language: | zh-TW |
Published: |
2004
|
Online Access: | http://ndltd.ncl.edu.tw/handle/51039934196387331071 |
Similar Items
-
Design of 10-bit, 20MHz sampling rate CMOS pipelined analog-to-digital converter
by: 林建邦
Published: (2001) -
8-bit, 80MHz Sampling Rate CMOS Pipeline Analog-to-Digital Converter
by: Kuo-Pin Lan, et al.
Published: (2002) -
Design of 10-bit 50MHz Pipelined Analog-to-Digital Converter
by: Cheng-Ming Ying, et al.
Published: (2003) -
A 10-bit 60MHz pipelined CMOS analog to digital converter
by: Sheng-Chuan Liang, et al.
Published: (1995) -
Design of a 10-bit 50MHz Pipelined Analog-to-Digital Converter
by: Chao I-Jen, et al.
Published: (2007)